\section{Previous Work}
\label{litReview}

The importance of improving the performance of Galois field arithmetic is evident by the existence of libraries devoted to speeding up the performance of Galois field arithmetic~\cite{PlankPFGA, AccGFA, luo2012}. These libraries make use of precomputed tables in order to do multiplication and division in $GF(2^w)$.  As pointed out by Kalcher and Lindenstruth in~\cite{AccGFA}, current Galois field implementations typically perform multiplication using pre-calculated lookup tables. However, since the memory system has become one of the major bottlenecks in current computers and table lookup requires large persistent data structures to be stored in memory, this method has severe scalability limitations. 

In addition to existing libraries, there are many research initiatives to implement new techniques to speed up Galois field arithmetic. Similar to our approach, the authors of~\cite{AccGFA} explore the use of vector architectures and graphics processing units (GPUs) to accelerate Galois arithmetic by eliminating table look ups.  Section~\ref{performance} discusses the results of their findings.  Also, the work in~\cite{optGFA} analyzes existing table-based methods and proposes the use of composite fields for more efficient computation over a Galois field.  Next, the authors in~\cite{support1} implement extension fields to speed up Galois field multiplication and division. 

While the results in~\cite{optGFA} show a dramatic improvement in throughput, the authors note that performance optimizing software is highly dependent on the system's underlying hardware and workload. Most importantly, the authors state that raw multiplication performance does not always reflect application performance. As a result, the authors of~\cite{optGFA} conclude that the use of composite fields for Galois field arithmetic requires less memory, but note that their study does not prove that one single approach works best for all applications of Galois field arithmetic across all architectures.  

Further, there are research initiatives to speed up specific computations in Galois field arithmetic and various aspects of erasure coding.  Specifically, the study found in~\cite{microsoft2} implements two greedy algorithms to speed up XOR-based Reed-Soloman codes. Next, the authors of~\cite{support2} apply optimized Cauchy Reed-Solomon codes to test the fault tolerance of network storage applications.  The technical report of this work is found in~\cite{PlankCauchy}.  The use of a class of binary maximum distance separable array codes to create more efficient and tolerable disk failures is presented in~\cite{support3}.

In response to the flurry of research in arithmetic techniques for erasure coding, the work found in~\cite{encdec} performs comparisons between a variety of implementations on encoding and decoding tasks.  The authors provide suggestions for the best performance in the following categories: RAID-6, applications for CRS versus RS codes, parameter selection for packet sizes, and minimizing the Cache/Memory Footprint.  Finally, the authors conclude that future research should be done in the area of special-purpose codes.  
